Interrupt Enable Clear register.
| MSTPENDINGCLR | Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. |
| MSTARBLOSSCLR | Master Arbitration Loss interrupt clear. |
| MSTSTSTPERRCLR | Master Start/Stop Error interrupt clear. |
| SLVPENDINGCLR | Slave Pending interrupt clear. |
| SLVNOTSTRCLR | Slave Not Stretching interrupt clear. |
| SLVDESELCLR | Slave Deselect interrupt clear. |
| MONRDYCLR | Monitor data Ready interrupt clear. |
| MONOVCLR | Monitor Overrun interrupt clear. |
| MONIDLECLR | Monitor Idle interrupt clear. |
| EVENTTIMEOUTCLR | Event time-out interrupt clear. |
| SCLTIMEOUTCLR | SCL time-out interrupt clear. |